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MC100LVEL34 3.3V ECL / 2, / 4, / 8 Clock Generation Chip
Description
The MC100LVEL34 is a low skew / 2, / 4, / 8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock; therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start-up, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as multiple LVEL34s in a system.
Features
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MARKING DIAGRAMS*
16 16 1 SO-16 D SUFFIX CASE 751B 100LVEL34G AWLYWW 1 16 16 1 TSSOP-16 DT SUFFIX CASE 948F 100 VL34 ALYW G G 1
* * * * * *
50 ps Typical Output-to-Output Skew Synchronous Enable/Disable Master Reset for Synchronization 1.5 GHz Toggle Frequency The 100 Series Contains Temperature Compensation. PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V VCC = 0 V with VEE = -3.0 V to -3.8 V Open Input Default State
A = Assembly Location L, WL = Wafer Lot Y = Year W, WW = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet.
* NECL Mode Operating Range:
* * LVDS Input Compatible * Pb-Free Packages are Available
(c) Semiconductor Components Industries, LLC, 2006
November, 2006 - Rev. 2
1
Publication Order Number: MC100LVEL34/D
MC100LVEL34
Table 1. PIN DESCRIPTION
Q0 1 Q Q0 2 R VCC 3 Q D 14 NC /2 15 16 VCC PIN CLK*, CLK** EN* EN MR* Q0, Q0 Q1, Q1 Q2, Q2 VBB Q1 4 Q Q1 5 R VCC 6 11 VBB /4 12 CLK 13 CLK VCC VEE NC FUNCTION ECL Diff Clock Inputs ECL Sync Enable ECL Master Reset ECL Diff /2 Outputs ECL Diff /4 Outputs ECL Diff /8 Outputs Reference Voltage Output Positive Supply Negative Supply No Connect
R
* Pins will default LOW when left open. ***Pins will default to VCC/2 when left open.
Table 2. FUNCTION TABLE
Q2 7 Q /8 Q2 8 R 9 VEE 10 MR CLK Z ZZ X EN L H X MR L L H FUNCTION Divide Hold Q0-3 Reset Q0-3
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Z = Low-to-High Transition ZZ = High-to-Low Transition
Figure 1. 16-Lead Pinout (Top View) and Logic Diagram
Table 3. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Pb Pkg Level 1 Level 1 Value 75 kW 37.5 kW > 2 kV > 200 V > 2 kV Pb-Free Pkg Level 1 Level 1
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) SOIC-16 TSSOP-16 Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in 210 Devices
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MC100LVEL34
Table 4. MAXIMUM RATINGS
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board 0 lfpm 500 lfpm Standard Board SOIC-16 SOIC-16 SOIC-16 TSSOP-16 TSSOP-16 TSSOP-16 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI v VCC VI w VEE Condition 2 Rating 6 -6 6 -6 50 100 0.5 -40 to +85 -65 to +150 100 60 33 to 36 138 108 33 to 36 265 265 Unit V V V V mA mA mA C C C/W C/W C/W C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Table 5. 100LVEL DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) Input HIGH Current Input LOW Current D D 0.5 -150 Min 40 2155 1355 2075 1355 1775 1.2 1875 Typ 50 2280 1570 Max 60 2405 1725 2420 1675 1975 3.3 150 0.5 -150 Min 40 2155 1355 2075 1355 1775 1.2 1875 25C Typ 50 2280 1570 Max 60 2405 1725 2420 1675 1975 3.3 150 0.5 -150 Min 42 2155 1355 2075 1355 1775 1.2 1875 85C Typ 52 2280 1570 Max 62 2405 1725 2420 1675 1975 3.3 150 Unit mA mV mV mV mV mV V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to -0.5 V. 3. All loading with 50 W to VCC - 2.0 V. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC100LVEL34
Table 6. 100LVEL DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -3.8 V to -3.0 V (Note 5)
-40C Symbol IEE IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Power Supply Current Output HIGH Voltage (Note 6) Output LOW Voltage (Note 6) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 7) Input HIGH Current Input LOW Current D D 0.5 -150 Min 23 40 -1145 -1945 -1225 -1945 -1525 -1425 VEE + 1.2 Typ 30 50 -1020 -1700 Max 40 60 -895 -1575 -880 -1625 -1325 0.0 Min 23 40 -1145 -1945 -1225 -1945 -1525 -1425 VEE + 1.2 25C Typ 30 50 -1020 -1700 Max 40 60 -895 -1575 -880 -1625 -1325 0.0 Min 23 42 -1145 -1945 -1225 -1945 -1525 -1425 VEE + 1.2 85C Typ 30 52 -1020 -1700 Max 40 62 -895 -1575 -880 -1625 -1325 0.0 Unit mA mA mV mV mV mV mV V
IIH IIL
150 0.5 -150
150 0.5 -150
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. 6. All loading with 50 W to VCC - 2.0 V. 7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 7. AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 8)
-40C Symbol fmax tPLH tPHL tJITTER tS tH tRR VPP tr tf Characteristic Maximum Toggle Frequency (Figure 4) Propagation Delay to Output CLK to Q0, Q1, Q2 MR to Q Min 1.5 550 500 650 600 <1 150 200 300 150 120 170 50 100 200 1000 400 150 200 300 150 140 180 1000 1000 Typ Max Min 1.5 600 550 700 650 <1 50 100 200 1000 400 150 200 300 150 160 200 1000 1000 25C Typ Max Min 1.5 650 600 750 700 <1 50 100 200 1000 400 1000 1000 85C Typ Max Unit GHz ps ps ps ps ps mV ps
Cycle-to-Cycle Jitter (Figure 4) Setup Time EN Hold Time EN Set/Reset Recovery Input Swing (Note 9) Output Rise/Fall Times Q (20% - 80%)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC - 2.0 V. 9. VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of 940.
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MC100LVEL34
There are two distinct functional relationships between the Master Reset and Clock:
Internal Clock Disabled MR CLK Q0 Q1 Q2 EN Internal Clock Enabled
CASE 1: If the MR is deasserted (H-L), while the Clock is still high, the outputs will follow the second ensuing clock rising edge.
Internal Clock Disabled MR CLK Q0 Q1 Q2 EN Internal Clock Enabled
CASE 2: If the MR is deasserted (H-L), after the Clock has transitioned low, the outputs will follow the third ensuing clock rising edge. Figure 2. Timing Diagrams
The EN signal will "freeze" the internal divider flip-flops on the first falling edge of CLK after its assertion. The internal divider flip-flops will maintain their state during the freeze. When EN is deasserted (LOW), and after the next falling edge of CLK, then the internal divider flip-flops will "unfreeze" and continue to their next state count with proper phase relationships.
TRR CLOCK CLOCK TRR
MR OUTPUT
MR OUTPUT
CASE 1 Figure 3. Reset Recovery Time
CASE 2
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MC100LVEL34
900 800 700 VOUTpp (mV) 600 500 400 300 200 100 0 0 JITTER OUT ps (RMS) B2 B4 / 8 9 8 7 6 5 4 3 2 1
500
1000 FREQUENCY (MHz)
1500
Figure 4. Fmax/Jitter
Q Driver Device Q
Zo = 50 W
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 2.0 V
Figure 5. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
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MC100LVEL34
ORDERING INFORMATION
Device MC100LVEL34D MC100LVEL34DG MC100LVEL34DR2 MC100LVEL34DR2G MC100LVEL34DT MC100LVEL34DTG MC100LVEL34DTR2 MC100LVEL34DTR2G Package SOIC-16 SOIC-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) TSSOP-16* TSSOP-16* TSSOP-16* TSSOP-16* Shipping 48 Units / Rail 48 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel 96 Units / Rail 96 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC100LVEL34
PACKAGE DIMENSIONS
SO-16 D SUFFIX CASE 751B-05 ISSUE J
9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-A-
16
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
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MC100LVEL34
PACKAGE DIMENSIONS
TSSOP-16 CASE 948F-01 ISSUE B
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K
2X
L/2
16
9
J1 B -U-
SECTION N-N J N
L
PIN 1 IDENT. 1 8
0.15 (0.006) T U
S
A -V-
N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
SOLDERING FOOTPRINT*
7.06 1
0.36
16X
16X
1.26
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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CCC EEE CCC EEE CCC
0.25 (0.010) M
K1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
0.65 PITCH
DIMENSIONS: MILLIMETERS
MC100LVEL34
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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